Recently, advanced SOI technology nodes are being used more extensively due to a number of advantages mainly related to the reduction of the power consumption, smaller silicion area, lower gate delay and reduced parasitic junction capacitance. Moreover, due to the completely isolated transistors, latch-up is no longer an issue.
However, SOI technology comes also with a few disadvantages such as the higher cost for starting material, floating body and history effects, increased self-heating issues and higher design complexity. Another main disadvantage is the fact that traditional snap-based ESD solutions have a much reduced (It2) failure current. This It2 reduction compared to bulk is related to the thin silicon film and the complete isolation of the transistors which limits the dissipation and transfer of the generated heat.
For ESD protection, the MOS device is often used in bipolar mode. Avalanche multiplication on the drain side of the MOS triggers the intrinsic parasitic bipolar device. The amount of current needed, and thus the amount of avalanche multiplication needed, scales inversely proportional with the resistance of the Pwell of NMOS (Nwell in case of PMOS) between pwell (Nwell) connection and the gate region. Since the avalanche multiplication causes heat, reducing the avalanche multiplication can increase the failure current It2 of the MOS device. Therefore, it is important to control the bulk resistance to adjust the ESD properties of the MOS device.
In most CMOS processes the bulk connection is created by adding guard rings around the MOS device. For example, a guard ring is a heavily p-doped region surrounding the MOS. This p-doped region, the same doping as the Pwell, connects the pwell with an external node. With this node the Pwell of the NMOS is controlled. In SOI technologies three methods exist. One such method includes a schematic to view layout of a single finger MOS device 100 having source region 102, drain region 104, and a gate region 106 disposed between the source 102 and the drain regions 104 as shown in FIG. 1. In this process, a bulk connection 108 is placed at the end of the gate 106. The gate 106 extension to the bulk connection 108 area is necessary to avoid isolating the bulk connection form the gate area with isolation such as a shallow trench isolation (STI) or deep trench isolation (DTI) or other isolations known to one skilled in the art. The disadvantage with this technique is that the bulk connection is only at the both sides of the gate. With large gate width only the side parts of the MOS has a good connection with the bulk connection. The middle part is connected through a large (well) resistance with the bulk connection.
A second technique is displayed in FIG. 2 which includes a schematic layout view and cross section view of a single finger MOS device 200 having source region 202, drain region 204, and a gate region 206 disposed between the source 202 and the drain regions 204. A bulk connection 208 is placed at the end of the gate 206. This technique includes an isolation between the gate area 206 and bulk connection 208 is used which does not reach to a buried oxide (BOX) 210. This isolation is commonly referred to as PTI (partial trench isolation) 212 as shown in FIG. 1. In some SOI technologies, an STI (Shallow trench isolation) 214 or another isolation can be used with the same effect as illustrated in FIG. 2. A very basic layout view and cross section are shown in FIG. 2. Note the difference between the PTI 212, which does not reach to the BOX 210, however, and STI 214 which does reach down to the BOX 210. However, in some technologies the STI does not reach to the box either. In this case there is no need for a separate PTI layer and STI can be used instead. The disadvantage of this technique is similar to the technique discussed in FIG. 1 that the bulk connection is only at the both sides of the gate. Another disadvantage is that an extra process option, for example PTI is needed. Since extra process steps are very costly, this technique is undesirable.
A third technique includes a schematic layout of a top view of a two finger MOS device 300 having a source regions 302, drain regions 304 and gate regions 306 disposed between the source 302 and the drain regions 304. This process includes interrupting the source 302 with a bulk connection area 308. Silicide shorts this region with the source 302. This is shown in FIG. 3, where there is bulk connection 308 through P+ area, interrupting the source 302 of the MOS device 300. The silicide layer connects the bulk P+ area with the source. The disadvantage if this technique is that the bulk connection is always shorten to the source. In some cases this is acceptable, but normally it is advantageous (improved triggering) if the bulk connection can be controlled in a different way then the shortening to source.
Therefore, a need exists to provide an improved technique enabling a better control of the bulk resistance to adjust the ESD properties for an improved performance of the MOS devices. Furthermore, it is advantageous to have a good bulk connection not only to control the bulk of one finger, but also to couple the different fingers (channel regions) together to improve multifinger triggering.